1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having a shallow trench isolation (STI).
2. Description of the Related Art
A complete circuit, such as an integrated circuit (IC), is usually composed of thousands of transistors. A shallow trench isolation (STI) serves as an isolation region to prevent a short circuit between two adjacent transistors. Such STI is formed by producing a shallow trench in a semiconductor substrate by anisotropically etching the semiconductor substrate using a silicon nitride layer as a hard mask, and then filling the shallow trench with an insulating layer.
The characteristics of an STI depend on whether the STI has a liner layer. However, a defect, such as a shallow pit, occurs in an STI that does not have a liner layer, due to subsequent oxidation. The defect degrades the electrical characteristics of the resultant device, and cause a leakage current in a junction region, i.e., adversely affects the isolation of the device. In addition, since the shallow trench formed in the substrate is angulated at its top corner, a gate oxide layer grows insufficiently or non-uniformly during a subsequent thermal oxidation process. Hence, the portion of the gate oxide layer formed on the top corner of the shallow trench is very thin. As a result, a breakdown voltage of the gate oxide layer on the active region becomes lower, and a parasitic current occurs in a transistor, thereby degrading the operability of the resultant device.
In an effort to solve these problems, an STI has been provided with a liner layer. FIGS. 1A to 1F illustrate a process of forming such a conventional STI having a liner layer.
Referring to FIG 1A, a semiconductor substrate 10 having a pad oxide layer 11 and a mask layer 12 formed thereon is provided. The semiconductor substrate is made of silicon and has a field region 10-1 and an active region 10-2. The pad oxide layer 11 and the mask layer 12 are patterned to form a shallow trench 13 in the substrate 10.
Referring to FIG 1B, a buffer oxide layer 14 is formed in the shallow trench 13, and then a liner layer 15 is formed to cover the buffer oxide layer 14. The buffer oxide layer 14 is formed by growing a thermal oxide layer on side portions and a bottom portion of the shallow trench 13. The buffer oxide layer 14 is provided to cure damage that has occurred during the process of etching the semiconductor substrate 10 to form the trench 13, and to prevent stress and a trap center from being generated between the liner layer 15 and the silicon substrate 10. The liner layer is generally made of a nitride.
Subsequently, as shown in FIG. 1C, the shallow trench 13 is filled with an insulating layer 18. Thereafter, as shown in FIG 1D, the liner layer 15 and the insulating layer 16 formed on the mask layer 12 are polished by a CMP process so as to planarize a surface of the substrate 10, until a predetermined thickness of the mask layer 12 remains.
Next, as shown in FIG. 1E, the mask layer 12 is removed. Finally, as shown in FIG. 1F, a wet-etching process is performed to remove the pad oxide layer 11. As a result, a shallow trench isolation (STI) 17 is formed to prevent defects that would otherwise occur due to a subsequent oxidation.
However, the conventional method of forming the STI has a problem in that when the mask layer 12 is removed, as shown in FIG. 1E, a portion of the liner layer 15 is also removed, thereby forming dents 18. In addition, as shown in FIG 1F, the dents 18 become deeper due to the wet-etching process performed to remove the pad oxide layer 11.
FIG. 2 is a photograph of an STI made according to the prior art. As can be seen in FIG. 2, very deep dents 28 are formed at the top corner of the shallow trench 23. In FIG. 2, reference numeral 25 denotes the liner layer.
FIG. 3 illustrates a gate oxide layer formed subsequent to the STI. After the STI 17 shown in FIG 1F is formed, a gate oxide layer 20 having a non-uniform thickness is formed on the semiconductor substrate 10. As can be seen in FIG. 3, the gate oxide layer 20 on a region adjacent to an angulated portion (i.e., top corner) of the trench 13 grows insufficiently or non-uniformly. In other words, a portion Tox 32 of the gate oxide layer 20 formed at the edges of active region 10-2 is thinner than a portion Tox 31 of the gate oxide layer 20 formed on the active region 10-2.
FIG. 4 is a photograph of the gate oxide layer illustrated in FIG. 3. FIG. 4 shows that the gate oxide layer on the active region is formed to a thickness of 360 Å, while the gate oxide layer on the edges of the active region is formed to an insufficient thickness of 79 Å.
The gate oxide layer having a non-uniform thickness lowers a breakdown voltage, and so a parasitic current occurs in a transistor, thereby degrading the operability of the resultant device.